The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As shown in FIGS. 1 and 2, conventional practices comprise depositing metal layer 11 on dielectric layer 10 which is typically formed on a semiconductor substrate containing an active region with transistors (not shown) After photolithography, etching is then conducted to form a patterned metal layer comprising metal features 11a, 11b, 11c and 11d with gaps therebetween. A dielectric material 12, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed, to enhance the dielectric properties of SOG. A layer of silicon dioxide is deposited by plasma enhanced chemical vapor deposition (PECVD) to cap the SOG layer and is subsequently planarized, as by CMP, before the next level of via and metal wiring is attempted.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole for a via is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature. Such a conventional technique is illustrated in FIG. 3, wherein metal feature 30 of a first patterned metal layer is formed on first dielectric layer 31 and exposed by through-hole 32 formed in second dielectric layer 33. In accordance with conventional practices, through-hole 32 is formed so that metal feature 30 encloses the entire bottom opening, thereby serving as a landing pad for metal plug 34 which fills through-hole 32 to form conductive via 35. Thus, the entire bottom surface of conductive via 35 is in direct contact with metal feature 30. Conductive via 35 electrically connects metal feature 30 and metal feature 36 which is part of a second patterned metal layer. As shown in FIGS. 2 and 3, the side edges of a metal feature or conductive line,. e.g., 30A, 30B, and 36A, and 36B, taper somewhat as a result of etching.
The reduction of design features to the range of 0.25 microns and under results in extremely high density. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high density requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height of the through-hole with respect to diameter of the through-hole. Electrically, this leads to a via with an unacceptably high resistance. Accordingly, conventional remedial techniques comprise purposely widening the diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a "borderless via", which also conserves chip real estate.
The formation of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture is absorbed during cleaning after forming a through-hole, thereby increasing the resistance of the via. Moreover, spiking can occur, i.e., unintended penetration of the metal plug to any active layer below the metal feature, causing an electrical short.
The use of a high density dielectric material, such as a high density plasma (HDP) oxide, appears promising as a substitute for SOG. HDP oxide is typically deposited by high density plasma chemical vapor deposition (HDP-CVD). See, for example, Liu et al., "Integrated HDP Technology for Sub-0.25 Micron Gap Fill", pp. 618-619; Bothra et al., "INTEGRATION OF 0.25 .mu.m THREE AND FIVE LEVEL INTERCONNECT SYSTEM FOR HIGH PERFORMANCE ASIC.", pp. 43-48; Wang et al., "Process Window Characterization of ULTIMA HDP-CVD.TM. USG Film", pp. 405-408; Saikawa et al., "High Density Plasma CVD for 0.3 .mu.m Device Application", pp. 69-75; Nguyen et al., "CHARACTERIZATION OF HIGH DENSITY PLASMA DEPOSITED SILICON OXIDE DIELECTRIC FOR 0.25 MICRON ULSI", pp. 69-74; all of which papers were presented at the Jun. 10-12, 1997 VMIC Conference, 1997 ISMIC.
HDP oxide advantageously exhibits superior gap filling properties and high stability vis-a-vis SOG and conventional PECVD oxides and, thus, easily fills gaps in a patterned metal layer with a 0.25 micron design rule. HDP oxide also exhibits superior qualities vis-a-vis SOG. For example, HDP oxide is denser and exhibits greater chemical stability and etch resistance than SOG. Accordingly, the use of HDP oxide appears promising for gap filling, particularly in manufacturing high density semiconductor devices with interconnection patterns having misaligned, i.e., borderless vias.
However, it was found that semiconductor devices having patterned metal layers gap filled with HDP oxide exhibit less electromigration resistance than those gap filled with SOG. Accordingly, there exists a need for methodology enabling the use of HDP oxide for gap filling patterned metal layers, particularly gaps consistent with a 0.25 micron design rule and under, without an attendant decrease in electromigration resistance.